Generally, nonvolatile memory devices can retain data even when the power is turned off. Therefore, nonvolatile memory devices are widely used as data storage devices for PC Bios, Set-tops, printers, network servers, and other such devices. Recently, nonvolatile memory devices have also been used in digital cameras and mobile phones.
One such nonvolatile memory device, is an Electrically Erasable Programmable Read-Only Memory (EEPROM). An EEPROM can electrically erase data of memory cells one at a time or on a sector basis. For a program operation, channel hot electrons are formed at a drain and electrons are accumulated in a floating gate, thus increasing the threshold voltage of the cell transistor.
For an erase operation, a high voltage is generated between a source and a floating gate and the electrons accumulated at the floating gate are discharged, thus decreasing the threshold voltage of the cell transistor.
Two examples of the typical cell structures of the EEPROM are an EPROM tunnel oxide (ETOX) cell having a simple stacked structure, and a split gate type cell having two transistors per cell.
In the case of the ETOX cell, a floating gate for storing electric charges and a control gate to which a driving voltage is applied are stacked. In the case of the spilt gate type cell, one memory cell includes two transistors, that is, a selection transistor for selecting a cell and a memory transistor for storing data.
The memory transistor includes a floating gate for storing the electric charges, a control gate for controlling the memory transistor, and a gate insulating layer interposed therebetween.
FIG. 1 is a plan view of a prior art flash memory device and FIG. 2 is a sectional view taken along line A-A′ of FIG. 1.
Referring to FIGS. 1 and 2, a field oxide layer 12 is formed in a semiconductor substrate 11 to define a field region and an active region in the substrate 11.
A floating gate 15 is formed over the active region and the field oxide region such that an edge of the floating gate 15 partially overlaps the field oxide layer 12. Also, a control gate 17 is formed on the floating gate 15 such that it overlaps the floating gate 15.
A tunneling oxide layer 14 is formed between the floating gate 15 and the semiconductor substrate 11, and an oxide-nitride-oxide (ONO) layer 16 is formed between the control gate 17 and the floating gate 15.
The floating gate 15 stores electric charges and the control gate 17 maintains a voltage of the floating gate 15.
A source region 18 and a drain region 19 are formed on both sides of the floating gate 15 and the control gate 17 in the active region of the semiconductor substrate 11, and a drain contact 20 is formed in the drain region 19.
FIGS. 3A to 3D are sectional views through line A-A′ of FIG. 1 illustrating a method of manufacturing a related prior art flash memory device.
Referring to FIG. 3A, a buffer oxide layer 13 is formed on the semiconductor substrate 11 and is selectively removed to expose a portion of the semiconductor substrate 11, which will be defined as a field region by a photo and etching process.
A trench is formed in the semiconductor substrate 11 using the buffer oxide layer 13 as a mask. Then, the trench is filled with an oxide layer to form a field oxide layer 12 having a Shallow Trench Isolation (STI) structure.
Then, impurity ions are implanted to form a well (not shown).
Referring to FIG. 3B, the buffer oxide layer 13 is removed and a tunneling oxide layer 14 is formed on the semiconductor substrate 11. Then, a first polysilicon layer 15a is deposited on the resulting structure.
Referring to FIG. 3C, a first polysilicon pattern 15b is formed by selectively etching the first polysilicon layer 15a using a photo and etching process such that the polysilicon remains on the active region of the semiconductor substrate 11 and a portion of adjacent field oxide layer 12.
Referring to, FIG. 3D, an ONO layer 16 and a second polysilicon layer are sequentially formed on the entire surface of the semiconductor substrate 11 and the first polysilicon pattern 15b. A photoresist (not shown) is coated on the semiconductor substrate 11 and then patterned to expose the second polysilicon layer in a direction crossing the active region.
Using the patterned photoresist as a mask, the polysilicon layer, the ONO layer 16, and the first polysilicon pattern 15b are etched to form a stacked gate having a floating gate 15 and a control gate 17.
Although not shown, the source region 18 and the drain region 19 are formed by implanting impurity ions into the active region of the semiconductor substrate 11 using the control gate 17 as a mask. Then, an interlayer insulating layer is formed on the entire surface of the resulting structure, and a drain contact 20 is formed on the interlayer insulating layer to connect the drain region 19 to a bit line (BL).
However, in forming the floating gate, a height difference problem occurs between a center portion and an edge portion of the floating gate due to the device isolation layer having an STI structure at the edge portion of the floating gate. Just as the floating gate is higher at its edge portion than at its center portion, the ONO layer formed on the floating gate experiences the height difference. This height difference can also be referred to as roughness.
Consequently, the uniformity of the conductive layer formed on the ONO layer is deteriorated, causing the degradation in the electric characteristics of the devices manufactured using the above described patterning technique.